Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

Product codes
ATSAM4S-WPIR-RD
Page of 1231
571
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
Figure 31-12. Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=0)
Figure 31-13. Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=1)
31.5.13.3Restrictions
Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR can be changed ONLY if the parallel 
capture mode is disabled at this time (PCEN = 0 in PIO_PCMR).
Frequency of PIO Controller clock must be strictly superior to two times the frequency of the clock of the 
device which generates the parallel data.
31.5.13.4Programming Sequence
Without PDC
1. Write PIO_PCIDR and PIO_PCIER in order to configure the parallel capture mode interrupt mask.
2. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to configure the parallel 
capture mode WITHOUT enabling the parallel capture mode. 
3. Write PIO_PCMR to set the PCEN bit to one in order to enable the parallel capture mode WITHOUT 
changing the previous configuration.
4. Wait for a data ready by polling the DRDY flag in PIO_PCISR or by waiting for the corresponding interrupt.
5. Check OVRE flag in PIO_PCISR.
0x23
0x34
0x45
0x12
0x56
0x67
0x78
0x89
0x6745_2301
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of  PIO_PCISR
MCK
0x23
0x34
0x45
0x12
0x56
0x67
0x78
0x89
0x7856_3412
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of  PIO_PCISR
MCK