Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

67

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

CONTROL

 Read

/Write

 0x00

0000000 

The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread 

mode.

Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception 

return.

Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control 

Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the 

EXC_RETURN value.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and 

exception handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:

• Use the MSR instruction to set the Active stack pointer bit to 1, see 

, or

• Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see 

.

Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures 

that instructions after the ISB execute using the new stack pointer. See 

31

30

29

28

27

26

25

24

–

23

22

21

20

19

18

17

16

–

15

14

13

12

11

10

9

8

–

7

6

5

4

3

2

1

0

–

–

SPSEL

nPRIV