Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all NPCS 

signals are high before and after each transfer.



: SPI exchanges data with only one peripheral.

Fixed peripheral select mode is enabled by writing the PS bit to zero in SPI_MR. In this case, the current 

peripheral is defined by the PCS field in SPI_MR and the PCS field in SPI_TDR has no effect.



 Data can be exchanged with more than one peripheral without having to 

reprogram the NPCS field in SPI_MR.

Variable peripheral select Mode is enabled by setting the PS bit to one in SPI_MR. The PCS field in 

SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for 

each new data. The value to write in SPI_TDR has the following format:

[xxxxxxx(7-bit) + LASTXFER(1-bit)

+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals the 

chip select to assert, as defined in 

 and LASTXFER bit at 0 or 1 

depending on the CSAAT bit.

Note:

1. Optional

CSAAT, LASTXFER and CSNAAT bits are discussed in 

.
If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, 

the user can use the SPIDIS command. After the end of the PDC transfer, it is necessary to wait for the 

TXEMPTY flag and then write SPIDIS into the SPI Control register (SPI_CR). This does not change the 

configuration register values). The NPCS is disabled after the last character transfer. Then, another PDC 

transfer can be started if the SPIEN has previously been written in SPI_CR.

In both Fixed and Variable peripheral select modes, the Peripheral DMA Controller (PDC) can be used to reduce 

processor overhead.
The fixed peripheral selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, 

as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the 

peripheral selection is modified, the SPI_MR must be reprogrammed.
The variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the 

SPI_MR. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the destination 

peripheral. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and 

LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to16) to be transferred through 

MISO and MOSI lines with the chip select configuration registers (SPI_CSRx). This is not the optimal means in 

DLYBCS

DLYBS

DLYBCT

DLYBCT

Chip Select 1

Chip Select 2

SPCK