Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
676
devices, SPI_CSR can be programmed with the Chip Select Not Active After Transfer (CSNAAT) bit to 1. This
allows the chip select lines to be de-asserted systematically during a time “DLYBCS” (the value of the CSNAAT bit
is taken into account only if the CSAAT bit is set to 0 for the same chip select).
shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.
Figure 33-11. Peripheral Deselection
33.7.3.10Mode Fault Detection
The SPI has the capability to operate in multi-master environment. Consequently, the NPCS0/NSS line must be
monitored. If one of the masters on the SPI bus is currently transmitting, the NPCS0/NSS line is low and the SPI
A
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
A
DLYBCS
DLYBCT
A
PCS = A
A
A
DLYBCT
A
A
CSAAT = 0 and CSNAAT = 0
DLYBCT
A
A
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS = A
DLYBCT
A
A
CSAAT = 0 and CSNAAT = 1
NPCS[0..n]
Write SPI_TDR
TDRE
PCS = A
DLYBCT
A
A
CSAAT = 0 and CSNAAT = 0