Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

686

 SPI_SR

0x40008010

Read-only  



0: No data has been received since the last read of SPI_RDR.
1: Data has been received and the received data has been transferred from the shift register to SPI_RDR since the last 

read of SPI_RDR.



0: Data has been written to SPI_TDR and not yet transferred to the shift register.
1: The last data written in the SPI_TDR has been transferred to the shift register. 
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.



0: No mode fault has been detected since the last read of SPI_SR.
1: A mode fault occurred since the last read of SPI_SR.



0: No overrun has been detected since the last read of SPI_SR.
1: An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the shift register since the last read of the SPI_RDR.



0: The Receive Counter register has not reached 0 since the last write in SPI_RCR

 or SPI_RNCR

1: The Receive Counter register has reached 0 since the last write in SPI_RCR

 or SPI_RNCR

.



0: The Transmit Counter register has not reached 0 since the last write in SPI_TCR

 or SPI_TNCR

1: The Transmit Counter register has reached 0 since the last write in SPI_TCR

 or SPI_TNCR

.



0: SPI_RCR

 or SPI_RNCR

 has a value other than 0.

1: Both SPI_RCR

 and SPI_RNCR

 have a value of 0.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

SPIENS

15

14

13

12

11

10

9

8

–

–

–

–

–

UNDES

TXEMPTY

NSSR

7

6

5

4

3

2

1

0

TXBUFE

RXBUFF

ENDTX

ENDRX

OVRES

MODF

TDRE

RDRF