Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

Product codes
ATSAM4S-WPIR-RD
Page of 1231
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
696
34.
Two-wire Interface (TWI)
34.1
Description
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock 
line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can 
be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time 
Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is 
programmable as a master or a slave with sequential or single-byte access. Multiple master capability is 
supported.
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is 
lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock 
frequencies.
 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I
2
C compatible 
device.
Note:
1. START + b000000001 + Ack + Sr
34.2
Embedded Characteristics
2 TWIs
Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
One, Two or Three Bytes for Slave Address
Sequential Read-write Operations
Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbit/s
General Call Supported in Slave mode
SMBUS Quick Command Supported in Master Mode
Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers
̶
One Channel for the Receiver, One Channel for the Transmitter
Note:
1. See 
 for details on compatibility with I²C Standard.
Table 34-1.
Atmel TWI compatibility with I
2
C Standard
I
2
C Standard
Atmel TWI
Standard Mode Speed (100 kHz)
Supported
Fast Mode Speed (400 kHz)
Supported
7 or 10 bits Slave Addressing
Supported
START BYTE
Not Supported
Repeated Start (Sr) Condition
Supported
ACK and NACK Management
Supported
Slope control and input filtering (Fast mode)
Not Supported
Clock stretching
Supported
Multi Master Capability
Supported