Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
703
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
Figure 34-8.
Master Write with One Byte Internal Address and Multiple Data Bytes
34.8.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-
bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in
this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the
data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the
byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been
received, the master sends an acknowledge condition to notify the slave that the data has been received except
for the last data, after the stop condition. See
. When the RXRDY bit is set in the status register, a
character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the
TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits
. When a multiple data byte read is performed, with or without
. For
Internal Address usage see
.
Figure 34-9.
Master Read with One Data Byte
A
DATA n
A
S
DADR
W
DATA n+1
A
P
DATA n+2
A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1)
Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD
IADR
A
TWCK
A
S
DADR
R
DATA
NA
P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD