Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
714
Figure 34-21. Programmer Sends Data While the Bus is Busy
Figure 34-22. Arbitration Cases
gives an example of read and write operations in Multi-master
mode.
TWCK
TWD
DATA sent by a master
STOP sent by the master
START sent by the TWI
DATA sent by the TWI
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is initiated
TWI DATA transfer
Transfer is kept
Bus is considered as free
TWCK
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is initiated
TWI DATA transfer
Transfer is kept
Bus is considered as free
Data from a Master
Data from TWI
S
0
S
0
0
1
1
1
ARBLST
S
0
S
0
0
1
1
1
TWD
S
0
0
1
1 1
1 1
Arbitration is lost
TWI stops sending data
P
S
0
1
P
0
1
1
1
1
Data from the master
Data from the TWI
Arbitration is lost
The master stops sending data
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
TWCK
TWD