Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

72

Notes: 1. See 

 for more information.

2. WT = Write through, no write allocate. WBWA = Write back, write allocate. See the 

 for more information.

The Cortex-M4 processor:



Prefetches instructions ahead of execution



Speculatively prefetches from branch target addresses.

The order of instructions in the program flow does not always guarantee the order of the corresponding memory 

transactions. This is because:



The processor can reorder some memory accesses to improve efficiency, providing this does not affect the 

behavior of the instruction sequence.



The processor has multiple bus interfaces



Memory or devices in the memory map have different wait states



Some memory accesses are buffered or speculative.

 describes the cases where the memory system guarantees the 

order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include 

memory barrier instructions to force that ordering. The processor provides the following memory barrier 

instructions:

The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before 

subsequent memory transactions. See 

The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete 

before subsequent instructions execute. See 

.

The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is 

recognizable by subsequent instructions. See 

.

Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by 

subsequent instructions.

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band 

regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions: 

0xA0000000–0xBFFFFFFF

External device

Device

Shareable

–

0xC0000000–0xDFFFFFFF

Non-shareable

0xE0000000–0xE00FFFFF

Private Peripheral 

Bus

Strongly-ordered

Shareable

–

0xE0100000–0xFFFFFFFF

Vendor-specific 

device

Device

–

–