Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
729
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
34.11.5 TWI Clock Waveform Generator Register
Name: TWI_CW
GR
Address:
0x40018010 (0), 0x4001C010 (1)
Access: Read-writ
e
Reset:
0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
CKDIV
15
14
13
12
11
10
9
8
CHDIV
7
6
5
4
3
2
1
0
CLDIV
t
low
CLDIV
(
2
CKDIV
×
(
) 4 )
+
t
MCK
×
=
t
high
CHDIV
(
2
CKDIV
×
(
) 4 )
+
t
MCK
×
=