Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
742
Figure 35-7.
Parity Error
35.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same
time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit
RSTSTA at 1.
Figure 35-8.
Receiver Framing Error
35.5.3 Transmitter
35.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and must be enabled before being used. The transmitter is
enabled by writing UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to
be written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a
character has been written in the Transmit Holding Register, the characters are completed before the transmitter is
actually stopped.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1.
This immediately stops the transmitter, whether or not it is processing characters.
35.5.3.2 Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the
format defined in UART_MR and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits,
from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as
shown in the following figure. The field PARE in UART_MR defines whether or not a parity bit is shifted out. When
a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
stop
D0
D1
D2
D3
D4
D5
D6
D7
P
S
URXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
D0
D1
D2
D3
D4
D5
D6
D7
P
S
URXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop