Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

Product codes
ATSAM4S-WPIR-RD
Page of 1231
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
756
36.
Universal Synchronous Asynchronous Receiver Transceiver (USART)
36.1
Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal 
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of 
stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun 
error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard 
facilitates communications with slow remote devices. Multidrop communications are also supported through 
address bit handling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485, and SPI buses, with ISO7816 T = 
0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking 
feature enables an out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the 
transmitter and from the receiver. The PDC provides  chained buffer management without any intervention of the 
processor.
36.2
Embedded Characteristics
Programmable Baud Rate Generator
5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
̶
1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
̶
Parity Generation and Error Detection
̶
Framing Error Detection, Overrun Error Detection
̶
MSB- or LSB-first
̶
Optional Break Generation and Detection
̶
By 8 or by 16 Over-sampling Receiver Frequency
̶
Optional Hardware Handshaking RTS-CTS
̶
Optional Modem Signal Management DTR-DSR-DCD-RI
̶
Receiver Time-out and Transmitter Timeguard
̶
Optional Multidrop Mode with Address Generation and Detection
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
̶
NACK Handling, Error Counter with Repetition and Iteration Limit
IrDA Modulation and Demodulation
̶
Communication at up to 115.2 Kbps
SPI Mode
̶
MASTER or Slave
̶
Serial Clock Programmable Phase and Polarity
̶
SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
Test Modes
̶
Remote Loopback, Local Loopback, Automatic Echo
Supports Connection of:
̶
Two Peripheral DMA Controller Channels (PDC)
Offers Buffer Transfer without Processor Intervention