Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
760
36.6
Product Dependencies
36.6.1 I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART
are not used by the application, they can be used for other purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the
hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled.
All the pins of the modems may or may not be implemented on the USART. Only USART1 fully equipped with all
All the pins of the modems may or may not be implemented on the USART. Only USART1 fully equipped with all
the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses
have no effect on the behavior of the USART.
36.6.2 Power Management
The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power
Management Controller (PMC) before using the USART. However, if the application does not require USART
operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will
resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
Configuring the USART does not require the USART clock to be enabled.
36.6.3 Interrupt
The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART
interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the
USART interrupt line in edge sensitive mode.
Table 36-3.
I/O Lines
Instance
Signal
I/O Line
Peripheral
USART0
CTS0
PA8
A
USART0
RTS0
PA7
A
USART0
RXD0
PA5
A
USART0
SCK0
PA2
B
USART0
TXD0
PA6
A
USART1
CTS1
PA25
A
USART1
DCD1
PA26
A
USART1
DSR1
PA28
A
USART1
DTR1
PA27
A
USART1
RI1
PA29
A
USART1
RTS1
PA24
A
USART1
RXD1
PA21
A
USART1
SCK1
PA23
A
USART1
TXD1
PA22
A
Table 36-4.
Peripheral IDs
Instance
ID
USART0
14
USART1
15