Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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The Cortex-M4 processor

 

sleep modes reduce the power consumption:



Sleep mode stops the processor clock



Deep sleep mode stops the system clock and switches off the PLL and flash memory.

The SLEEPDEEP bit of the SCR selects which sleep mode is used; see 

. 

This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep 

mode.

This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor. 

Therefore, the software must be able to put the processor back into sleep mode after such an event. A program 

might have an idle loop to put the processor back to sleep mode. 

The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a 

WFI instruction it stops executing instructions and enters sleep mode. See 

 for more information.

The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event 

register. When the processor executes a WFE instruction, it checks this register:



If the register is 0, the processor stops executing instructions and enters sleep mode



If the register is 1, the processor clears the register to 0 and continues executing instructions without 

entering sleep mode.

See 

 for more information.

If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception 

handler, it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that 

only require the processor to run when an exception occurs.

The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.

Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception 

entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it 

executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an 

interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes 

up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information 

about PRIMASK and FAULTMASK, see 

.

The processor wakes up if:



It detects an exception with sufficient priority to cause an exception entry



It detects an external event signal. See 



In a multiprocessor system, another processor in the system executes an SEV instruction.