Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

888

After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus 

protocol. Each message is represented by one of the following tokens:



Command—A command is a token that starts an operation. A command is sent from the host either to a 

single card (addressed command) or to all connected cards (broadcast command). A command is 

transferred serially on the CMD line.



Response—A response is a token which is sent from an addressed card or (synchronously) from all 

connected cards to the host as an answer to a previously received command. A response is transferred 

serially on the CMD line.



Data—Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.

Card addressing is implemented using a session address assigned during the initialization phase by the bus 

controller to all currently connected cards. Their unique CID number identifies individual cards.
The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System 

Specification. See also Table 38-6 on page 889.
High Speed MultiMedia Card bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a response token. 

In addition, some operations have a data token; the others transfer their information directly within the command or 

response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines 

are transferred synchronous to the clock HSMCI clock.
Two types of data transfer commands are defined:



Sequential commands—These commands initiate a continuous data stream. They are terminated only when 

a stop command follows on the CMD line. This mode reduces the command overhead to an absolute 

minimum.



Block-oriented commands—These commands send a data block succeeded by CRC bits.

Both read and write operations allow either single or multiple block transmission. A multiple block transmission is 

terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block 

transmission has a pre-defined block count (See “Data Transfer Operation” on page 891.).
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations.

After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR.
The PWSEN bit saves power by dividing the HSMCI clock by 2

PWSDIV 

+ 1 when the bus is inactive.

The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI 

clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System 

Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI 

Command Register (HSMCI_CMDR). The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:

CMD

S T

Content

CRC

E Z

******

Z

S T

CID 

Content

Z

Z

Z