Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

903

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

 HS

MCI_MR

0x40000004

 Read

/Write

This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 926.

High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).

High Speed MultiMedia Card Interface clock is divided by 2

(PWSDIV)

 + 1 when entering Power Saving Mode.

 This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN 

bit).

Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data 

integrity, not bandwidth.
0: Disables Read Proof.
1: Enables Read Proof.

Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee 

data integrity, not bandwidth.
0: Disables Write Proof.
1: Enables Write Proof.

Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be 

supported.
Warning:

 BLKLEN value depends on FBYTE.

0: Disables Force Byte Transfer.
1: Enables Force Byte Transfer.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

PDCMODE

PADV

FBYTE

WRPROOF

RDPROOF

PWSDIV

7

6

5

4

3

2

1

0

CLKDIV