Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

911

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

 HS

MCI_CSTOR

0x4000001C

 Read

/Write  

This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 926.

This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. 

Its value is calculated by (CSTOCYC x Multiplier).

This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. 

Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data 

transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If 

a non-DATA ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the comple-

tion signal.
Multiplier is defined by CSTOMUL as shown in the following table:

If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag 

(CSTOE) in the HSMCI Status Register (HSMCI_SR) rises.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

–

CSTOMUL

CSTOCYC

0

1

CSTOCYC x 1

1

16

CSTOCYC x 16

2

128

CSTOCYC x 128

3

256

CSTOCYC x 256

4

1024

CSTOCYC x 1024

5

4096

CSTOCYC x 4096

6

65536

CSTOCYC x 65536

7

1048576

CSTOCYC x 1048576