Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

915

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

 HS

MCI_SR

0x40000040

 Read

-only 

0: A command is in progress.
1: The last command has been sent. Cleared when writing in the HSMCI_CMDR.

0: Data has not yet been received since the last read of HSMCI_RDR.
1: Data has been received since the last read of HSMCI_RDR.

0: The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.
1: The last data written in HSMCI_TDR has been transferred in the Shift Register.

This flag must be used only for Write Operations.
0: A data block transfer is not yet finished. Cleared when reading the HSMCI_SR.
1: A data block transfer has ended, including the CRC16 Status transmission.

the flag is set for each transmitted CRC Status.
Refer to the MMC or SD Specification for more details concerning the CRC Status.

0: No data transfer in progress.
1: The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.

A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data 

transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data 

line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data 

transfer block length becomes free.
Refer to the MMC or SD Specification for more details concerning the busy behavior.

31

30

29

28

27

26

25

24

UNRE

OVRE

ACKRCVE

ACKRCV

XFRDONE

FIFOEMPTY

–

–

23

22

21

20

19

18

17

16

CSTOE

DTOE

DCRCE

RTOE

RENDE

RCRCE

RDIRE

RINDE

15

14

13

12

11

10

9

8

TXBUFE

RXBUFF

CSRCV

SDIOWAIT

–

–

–

SDIOIRQA

7

6

5

4

3

2

1

0

ENDTX

ENDRX

NOTBUSY

DTIP

BLKE

TXRDY

RXRDY

CMDRDY