Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

942

 (PWM_SCUC) is set to ‘1’ (see “Method 1: Manual write of 



Method 2 (UPDM = 1): The period value, the duty-cycle values, the dead-time values and the update period 

value must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx, 

PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is 

triggered at the next PWM period as soon as the bit UPDULOCK in the PWM_SCUC register is set to ‘1’. 

The update of the duty-cycle values and the update period value is triggered automatically after an update 

period defined by the field UPR in the 

 (PWM_SCUP) (see 

“Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 943).



Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous 

channels are written by the Peripheral DMA Controller (PDC) (see “Method 3: Automatic write of duty-cycle 

values and automatic trigger of the update” on page 944). The user can choose to synchronize the PDC 

transfer request with a comparison match (see 

), by the fields 

PTRM and PTRCS in the PWM_SCM register.

In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by 

writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and 

PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK in the PWM_SCUC register which allows to update 

synchronously (at the same PWM period) the synchronous channels:



If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels.



If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.

After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
Sequence for Method 1:

Period Value
(PWM_CPRDUPDx)

Write by the CPU

Update is triggered at the

next PWM period as soon as

the bit UPDULOCK is set to ‘1’

Dead-Time Values 

(PWM_DTUPDx)

Write by the CPU

Update is triggered at the

next PWM period as soon as

the bit UPDULOCK is set to ‘1’

Duty-Cycle Values 

(PWM_CDTYUPDx)

Write by the CPU

Write by the CPU

Write by the PDC

Update is triggered at the next 

PWM period as soon as the bit 

UPDULOCK is set to ‘1’

Update is triggered at the next

PWM period as soon as the update period

counter has reached the value UPR

Update Period Value
(PWM_SCUPUPD)

Not applicable

Write by the CPU

Not applicable

Update is triggered at the next

PWM period as soon as the update period

counter has reached the value UPR