Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
972
39.7.16 PWM Interrupt Status Register 2
Name:
PWM_ISR2
Address:
0x40020040
Access:
Read-only
• WRDY: Write Ready for Synchronous Channels Update
0: New duty-cycle and dead-time values for the synchronous channels cannot be written.
1: New duty-cycle and dead-time values for the synchronous channels can be written.
1: New duty-cycle and dead-time values for the synchronous channels can be written.
• ENDTX: PDC End of TX Buffer
0: The Transmit Counter register has not reached 0 since the last write of the PDC.
1: The Transmit Counter register has reached 0 since the last write of the PDC.
1: The Transmit Counter register has reached 0 since the last write of the PDC.
• TXBUFE: PDC TX Buffer Empty
0: PWM_TCR or PWM_TCNR has a value other than 0.
1: Both PWM_TCR and PWM_TCNR have a value other than 0.
1: Both PWM_TCR and PWM_TCNR have a value other than 0.
• UNRE: Synchronous Channels Update Underrun Error
0: No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
1: At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
1: At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
• CMPMx: Comparison x Match
0: The comparison x has not matched since the last read of the PWM_ISR2 register.
1: The comparison x has matched at least one time since the last read of the PWM_ISR2 register.
1: The comparison x has matched at least one time since the last read of the PWM_ISR2 register.
• CMPUx: Comparison x Update
0: The comparison x has not been updated since the last read of the PWM_ISR2 register.
1: The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.
1: The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.
Note: Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CMPU7
CMPU6
CMPU5
CMPU4
CMPU3
CMPU2
CMPU1
CMPU0
15
14
13
12
11
10
9
8
CMPM7
CMPM6
CMPM5
CMPM4
CMPM3
CMPM2
CMPM1
CMPM0
7
6
5
4
3
2
1
0
–
–
–
–
UNRE
TXBUFE
ENDTX
WRDY