Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
997
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
39.7.39 PWM Channel Period Register
Name:
PWM_CPRDx [x=0..3]
Address:
0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3]
Access:
Read/Write
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the
.
Only the first 16 bits (channel counter size) are significant.
Only the first 16 bits (channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
X
CPRD
×
(
)
MCK
-------------------------------
CRPD
DIVA
×
(
)
MCK
------------------------------------------
CRPD
DIVB
×
(
)
MCK
------------------------------------------
2
X
CPRD
×
×
(
)
MCK
----------------------------------------
2
CPRD
DIVA
×
×
(
)
MCK
---------------------------------------------------
2
CPRD
×
DIVB
×
(
)
MCK
---------------------------------------------------