Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro. 

Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other errors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.