Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

gate to the interrupt controller. However, the corresponding bit in ISR will be set, and
EIC_WAKE will be set.

If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an
external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR.

In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so
spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The syn-
chronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the
interrupt controller by two cycles of CLK_SYNC, see 

 and 

 for examples (FILTER off).

It is also possible to apply a filter on EXTINTn by writing a one to INTn bit in the FILTER register.
This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest
three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of
the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see 

 and 

 for examples (FILTER on).

Figure 11-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge

Figure 11-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge

EXTINTn/NMI

CLK_SYNC

ISR.INTn:

FILTER off

ISR.INTn:

FILTER on

EXTINTn/NMI

CLK_SYNC

ISR.INTn:

FILTER off

ISR.INTn:

FILTER on