Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
151
32072H–AVR32–10/2012
AT32UC3A3
3.
End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst.
4.
Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that
the current master access is too long and must be broken.
the current master access is too long and must be broken.
• Undefined Length Burst Arbitration
In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix pro-
vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end
of burst is used as a defined length burst transfer and can be selected from among the following
five possibilities:
vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end
of burst is used as a defined length burst transfer and can be selected from among the following
five possibilities:
1.
Infinite: No predicted end of burst is generated and therefore INCR burst transfer will
never be broken.
never be broken.
2.
One beat bursts: Predicted end of burst is generated at each single transfer inside the
INCP transfer.
INCP transfer.
3.
Four beat bursts: Predicted end of burst is generated at the end of each four beat
boundary inside INCR transfer.
boundary inside INCR transfer.
4.
Eight beat bursts: Predicted end of burst is generated at the end of each eight beat
boundary inside INCR transfer.
boundary inside INCR transfer.
5.
Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat
boundary inside INCR transfer.
boundary inside INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers
(MCFG).
(MCFG).
• Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a
very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches
zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word
transfer.
very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches
zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word
transfer.
13.4.2.2
Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master requests arise at the same time,
the master with the lowest number is first serviced, then the others are serviced in a round-robin
manner.
the same slave in a round-robin manner. If two or more master requests arise at the same time,
the master with the lowest number is first serviced, then the others are serviced in a round-robin
manner.
There are three round-robin algorithms implemented:
1.
Round-Robin arbitration without default master
2.
Round-Robin arbitration with last default master
3.
Round-Robin arbitration with fixed default master
• Round-Robin Arbitration without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
requests from different masters to the same slave in a pure round-robin manner. At the end of