Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Accesses to unused areas returns an error result to the master requesting such an access.

The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data master interface.

Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, HMATRIX
SCFG4 register is associated with the Embedded CPU SRAM Slave Interface.

High Speed Bus masters

CPU Data

CPU Instruction

CPU SAB

PDCA

DMACA HSB Master 1

DMACA HSB Master 2

USBB DMA

High Speed Bus slaves

Internal Flash

HSB-PB Bridge A

HSB-PB Bridge B

AES

Embedded CPU SRAM 

USBB DPRAM

EBI

DMACA Slave

HRAMC0

HRAMC1