Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS

The write protocol is similar to the read protocol. It is depicted in 

. The

write cycle starts with the address setting on the memory address bus.

The NWE signal is characterized by a setup timing, a pulse width and a hold timing.

1.

NWESETUP: the NWE setup time is defined as the setup of address and data before 
the NWE falling edge.

2.

NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE 
rising edge.

3.

NWEHOLD: the NWE hold time is defined as the hold time of address and data after 
the NWE rising edge.

The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3.

The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined.

1.

NCSWRSETUP: the NCS setup time is defined as the setup time of address before the 
NCS falling edge. 

2.

NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS 
rising edge;

3.

NCSWRHOLD: the NCS hold time is defined as the hold time of address after the NCS 
rising edge.

CLK_SMC

A[AD_MSB:2]

NBS0, NBS1, 

A0, A1

NRD

NCS

D[15:0]

t

PACC

Data Sampling