Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
193
32072H–AVR32–10/2012
AT32UC3A3
15.6.5
Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
avoid bus contention or operation conflict.
15.6.5.1
Chip select wait states
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the deactivation of one device and the
activation of the next one.
cycle ensures that there is no bus contention between the deactivation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..5], NRD lines are all set to high level.
NWR3, NCS[0..5], NRD lines are all set to high level.
illustrates a chip select wait state between access on Chip Select 0
(NCS0) and Chip Select 2 (NCS2).
Figure 15-15. Chip Select Wait State Between a Read Access on NCS0 and a Write Access on
NCS2
15.6.5.2
Early read wait state
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
CLK_SMC
_MSB:2]
, NBS1,
, A1
NRD
NWE
NCS0
NCS2
D[15:0]
NRDCYCLE
Read to Write
Wait State
Chip Select
Wait State
NWECYCLE