Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
201
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on
the Same Chip Select.
15.6.7
External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The External Wait Mode field of the MODE register (MODE.EXNWMODE) on the corresponding
chip select must be written to either two (frozen mode) or three (ready mode). When the
MODE.EXNWMODE field is written to zero (disabled), the NWAIT signal is simply ignored on
the corresponding chip select. The NWAIT signal delays the read or write operation in regards to
the read or write controlling signal, depending on the read and write modes of the corresponding
chip select.
The External Wait Mode field of the MODE register (MODE.EXNWMODE) on the corresponding
chip select must be written to either two (frozen mode) or three (ready mode). When the
MODE.EXNWMODE field is written to zero (disabled), the NWAIT signal is simply ignored on
the corresponding chip select. The NWAIT signal delays the read or write operation in regards to
the read or write controlling signal, depending on the read and write modes of the corresponding
chip select.
15.6.7.1
Restriction
When one of the MODE.EXNWMODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in
Page Mode (
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in
Page Mode (
), or in Slow Clock Mode (
).
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
15.6.7.2
Frozen mode
When the external device asserts the NWAIT signal (active low), and after internal synchroniza-
tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC com-
pletes the access, resuming the access from the point where it was stopped. See
tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC com-
pletes the access, resuming the access from the point where it was stopped. See
. This mode must be selected when the external device uses the NWAIT signal to
delay the access and to freeze the SMC.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Write2 controlling
signal(NWE)
D[15:0]
Read1 hold = 1
TDFCYCLES = 5
Read1 cycle
TDFCYCLES = 5
Read to Write
Wait State
4 TDF WAIT STATES
Write2 setup = 1
Write 2 cycle
TDFMODE=0
(optimization disabled)