Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.

Debug state can be entered as described in the AVR32UC Technical Reference Manual.

Debug state is exited by the retd instruction.

The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.

System Registers

Reg #

Address

Name

Function

0

0

SR

Status Register

1

4

EVBA

Exception Vector Base Address

2

8

ACBA

Application Call Base Address

3

12

CPUCR

CPU Control Register

4

16

ECR

Exception Cause Register

5

20

RSR_SUP

Unused in AVR32UC

6

24

RSR_INT0

Unused in AVR32UC

7

28

RSR_INT1

Unused in AVR32UC

8

32

RSR_INT2

Unused in AVR32UC

9

36

RSR_INT3

Unused in AVR32UC

10

40

RSR_EX

Unused in AVR32UC

11

44

RSR_NMI

Unused in AVR32UC

12

48

RSR_DBG

Return Status Register for Debug mode

13

52

RAR_SUP

Unused in AVR32UC

14

56

RAR_INT0

Unused in AVR32UC

15

60

RAR_INT1

Unused in AVR32UC

16

64

RAR_INT2

Unused in AVR32UC

17

68

RAR_INT3

Unused in AVR32UC

18

72

RAR_EX

Unused in AVR32UC

19

76

RAR_NMI

Unused in AVR32UC

20

80

RAR_DBG

Return Address Register for Debug mode

21

84

JECR

Unused in AVR32UC

22

88

JOSP

Unused in AVR32UC

23

92

JAVA_LV0

Unused in AVR32UC

24

96

JAVA_LV1

Unused in AVR32UC

25

100

JAVA_LV2

Unused in AVR32UC