Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
286
32072H–AVR32–10/2012
AT32UC3A3
18.7
User Interface
18.7.1
Memory Map Overview
The channels are mapped as shown in
. Each channel has a set of configuration reg-
isters, shown in
, where n is the channel number.
18.7.2
Channel Memory Map
Note:
1. The reset values are device specific. Please refer to the Module Configuration section at the
end of this chapter.
Table 18-1.
PDCA Register Memory Map
Address Range
Contents
0x000 - 0x03F
DMA channel 0 configuration registers
0x040 - 0x07F
DMA channel 1 configuration registers
...
...
(0x000 - 0x03F)+m*0x040
DMA channel m configuration registers
0x800-0x830
Performance Monitor registers
0x834
Version register
Table 18-2.
PDCA Channel Configuration Registers
Offset
Register
Register Name
Access
Reset
0x000
+ n*0x040
Memory Address Register
MAR
Read/Write
0x00000000
0x004
+ n*0x040
Peripheral Select Register
PSR
Read/Write
0x008
+ n*0x040
Transfer Counter Register
TCR
Read/Write
0x00000000
0x00C
+ n*0x040
Memory Address Reload Register
MARR
Read/Write
0x00000000
0x010
+ n*0x040
Transfer Counter Reload Register
TCRR
Read/Write
0x00000000
0x014
+ n*0x040
Control Register
CR
Write-only
0x00000000
0x018
+ n*0x040
Mode Register
MR
Read/Write
0x00000000
0x01C
+ n*0x040
Status Register
SR
Read-only
0x00000000
0x020
+ n*0x040
Interrupt Enable Register
IER
Write-only
0x00000000
0x024
+ n*0x040
Interrupt Disable Register
IDR
Write-only
0x00000000
0x028
+ n*0x040
Interrupt Mask Register
IMR
Read-only
0x00000000
0x02C
+ n*0x040
Interrupt Status Register
ISR
Read-only
0x00000000