Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
316
32072H–AVR32–10/2012
AT32UC3A3
19. DMA Controller (DMACA)
Rev: 2.0.6.6
19.1
Features
•
2 HSB Master Interfaces
•
4 Channels
•
Software and Hardware Handshaking Interfaces
–
8 Hardware Handshaking Interfaces
•
Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
•
Single-block DMA Transfer
•
Multi-block DMA Transfer
– Linked Lists
– Auto-Reloading
– Contiguous Blocks
•
DMA Controller is Always the Flow Controller
•
Additional Features
– Scatter and Gather Operations
– Channel Locking
– Bus Locking
– FIFO Mode
– Pseudo Fly-by Operation
19.2
Overview
The DMA Controller (DMACA) is an HSB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more System Bus. One channel is
required for each source/destination pair. In the most basic configuration, the DMACA has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two System Bus transfers are required for each DMA data transfer. This is
also known as a dual-access transfer.
source peripheral to a destination peripheral over one or more System Bus. One channel is
required for each source/destination pair. In the most basic configuration, the DMACA has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two System Bus transfers are required for each DMA data transfer. This is
also known as a dual-access transfer.
The DMACA is programmed via the HSB slave interface.