Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These regis-
ters, along with the CFGx register, are used by the DMACA to set up and describe the block
transfer. 

In this case, the DMACA re-programs the channel registers prior to the start of each block by
fetching the block descriptor for that block from system memory. This is known as an LLI update.

DMACA block chaining is supported by using a Linked List Pointer register (LLPx) that stores the
address in memory of the next linked list item. Each LLI (block descriptor) contains the corre-
sponding block descriptor (SARx, DARx, LLPx, CTLx).

To set up block chaining, a sequence of linked lists must be programmed in memory.

The SARx, DARx, LLPx and CTLx registers are fetched from system memory on an LLI update.
The updated contents of the CTLx register are written back to memory on block completion. 

 shows how to use chained linked lists in memory to define multi-block

transfers using block chaining.

The Linked List multi-block transfers is initiated by programming LLPx with LLPx(0) (LLI(0) base
address) and CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN.

Figure 19-7. Multi-block Transfer Using Linked Lists  

System Memory

SARx

DARx

LLPx(1)

CTLx[31..0]

CTLx[63..32]

SARx

DARx

LLPx(2)

CTLx[31..0]

CTLx[63..32]

LLPx(0)

LLPx(2)

LLPx(1)

LLI(0)

LLI(1)