Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
334
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-10. DMA Transfer Flow for Source and Destination Linked List Address
19.10.1.3
Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4)
1.
Read the Channel Enable register to choose an available (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
3.
Program the following channel registers:
Channel enabled by
software
LLI Fetch
Hardware reprograms
SARx, DARx, CTLx, LLPx
DMAC block transfer
Source/destination
status fetch
Is DMAC in
Row1 of
DMAC State Machine Table?
Channel Disabled by
hardware
Block Complete interrupt
generated here
generated here
DMAC transfer Complete
interrupt generated here
interrupt generated here
yes
no