Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
353
32072H–AVR32–10/2012
AT32UC3A3
19.12.4
Control Register for Channel x Low
Name: CTLxL
Access Type: Read/Write
Offset:
0x018 + [x * 0x58]
Reset Value:
0x00304801
This register contains fields that control the DMA transfer. The CTLxL register is part of the block descriptor (linked list item)
when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is
enabled.
when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is
enabled.
• LLP_SRC_EN
Block chaining is only enabled on the source side if the LLP_SRC_EN field is high and LLPx.LOC is non-zero.
• LLP_DST_EN
Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx.LOC is non-zero.
• SMS: Source Master Select
Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from
31
30
29
28
27
26
25
24
LLP_SRC_E
N
LLP_DST_E
N
SMS
DMS[1]
23
22
21
20
19
18
17
16
DMS[0]
TT_FC
DST_GATHE
R_EN
SRC_GATHE
R_EN
SRC_MSIZE
[2]
15
14
13
12
11
10
9
8
SRC_MSIZE[1:0]
DEST_MSIZE
SINC
DINC[1]
7
6
5
4
3
2
1
0
DINC[0]
SRC_TR_WIDTH
DST_TR_WIDTH
INT_EN
Table 19-4.
Source Master Select
SMS
HSB Master
0
HSB master 1
1
HSB master 2
Other
Reserved