Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
366
32072H–AVR32–10/2012
AT32UC3A3
19.12.12 Interrupt Status Registers
Name:
StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr
Access Type:
Read-only
Offset:
0x2E8, 0x2F0, 0x2F8, 0x300, 0x308
Reset Value:
0x00000000
• STATUS[3:0]
All interrupt events from all channels are stored in these Interrupt Status Registers after masking: StatusTfr, StatusBlock,
StatusSrcTran, StatusDstTran, StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, Sta-
tusTfr[2] is Channel 2’s status transfer complete interrupt.The contents of these registers are used to generate the interrupt
signals leaving the DMACA.
StatusSrcTran, StatusDstTran, StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, Sta-
tusTfr[2] is Channel 2’s status transfer complete interrupt.The contents of these registers are used to generate the interrupt
signals leaving the DMACA.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
STATUS3
STATUS2
STATUS1
STATUS0