Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
4
32072H–AVR32–10/2012
AT32UC3A3
2.
Overview
2.1
Block Diagram
Figure 2-1.
Block Diagram
AVR32UC
CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
TIMER/COUNTER
0/1
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
PERIPHERAL
DMA
CONTROLLER
256/128/64
KB
FLASH
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
ME
MO
R
Y I
N
TE
R
FA
C
E
S
M
M
M
M
M
S
S
S
S
S
M
EXTERNAL
INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
BUS MATRIX
FAST GPIO
GE
N
E
RA
L P
U
RP
OS
E
IO
s
64 KB
SRAM
G
E
NE
RA
L P
URPOS
E
IO
s
PA
PB
PC
PX
PB
PC
PX
A[2..0]
B[2..0]
B[2..0]
CLK[2..0]
EXTINT[7..0]
SCAN[7..0]
NMI
GCLK[3..0]
XIN32
XOUT32
XIN0
XOUT0
PA
PB
PC
PX
PB
PC
PX
RESET_N
E
X
TE
R
NAL
BUS I
N
TE
RF
ACE
(S
D
R
AM
, S
TA
TI
C
ME
MOR
Y
, C
O
MP
A
C
T
FL
ASH
& N
AND
FL
ASH
)
CAS
RAS
SDA10
SDCK
SDCKE
SDWE
NCS[5..0]
NRD
NWAIT
NWE0
DATA[15..0]
USB HS
INTERFACE
DMA
ID
VBOF
DMFS, DMHS
32 KHz
OSC
115 kHz
RCSYS
OSC0
PLL0
USART3
SERIAL
PERIPHERAL
INTERFACE 0/1
TWO-WIRE
INTERFACE 0/1
DM
A
DM
A
DM
A
RXD
TXD
TXD
CLK
MISO, MOSI
NPCS[3..1]
TWCK
TWD
USART1
DM
A
RXD
TXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
USART0
USART2
USART2
DM
A
RXD
TXD
TXD
CLK
RTS, CTS
SYNCHRONOUS
SERIAL
CONTROLLER
DM
A
TX_CLOCK, TX_FRAME_SYNC
RX_DATA
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
ANALOG TO
DIGITAL
CONVERTER
DM
A
AD[7..0]
WATCHDOG
TIMER
XIN1
XOUT1
OSC1
PLL1
SPCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
TCK
TDO
TDO
TDI
TMS
POWER
MANAGER
RESET
CONTROLLER
ADDR[23..0]
SLEEP
CONTROLLER
CLOCK
CONTROLLER
CLOCK
GENERATOR
FL
ASH
CO
N
TRO
LL
E
R
CONFIGURATION REGISTERS BUS
MEMORY PROTECTION UNIT
PB
PB
HSB
HSB
NWE1
NWE3
NWE3
PB
A
PB
B
NPCS0
LOCAL BUS
INTERFACE
INTERFACE
AUDIO
BITSTREAM
DAC
DM
A
DATA[1..0]
DATAN[1..0]
M
MULTIMEDIA CARD
& MEMORY STICK
INTERFACE
CLK
CMD[1..0]
DATA[15..0]
DM
A
S
AES
DM
A
CFCE1
CFCE2
CFCE2
CFRW
NANDOE
NANDWE
32KB RAM
32KB RAM
HR
A
M
0/
1
DPFS, DPHS
USB_VBIAS
USB_VBUS
USB_VBUS
S
S
VDDIN
VDDCORE
GNDCORE
DMACA
1V8
Regulator
TWALM