Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

   // Set R0 to GPIO base address

   mov    R0, LO(AVR32_GPIO_ADDRESS)

   orh    R0, HI(AVR32_GPIO_ADDRESS)

   // Enable GPIO control of pin 0-8

   mov    R1, 0xFF

   st.w   R0[AVR32_GPIO_GPERS], R1

   // Set initial value of port

   mov    R2, 0x01

   st.w   R0[AVR32_GPIO_OVRS], R2

   // Set up toggle value. Two pins are toggled

   // in each round. The bit that is currently set,

   // and the next bit to be set.

   mov    R2, 0x0303

   orh    R2, 0x0303

loop:

   // Only change 8 LSB

   mov    R3, 0x00FF

   and    R3, R2

   st.w   R0[AVR32_GPIO_OVRT], R3

   rol    R2

   rcall  delay

   rjmp   loop

It is assumed in this example that a subroutine "delay" exists that returns after a given time.

The example below shows how to configure a peripheral module to control I/O pins. It assumed
in this example that the USART receive pin (RXD) is connected to PC16 and that the USART
transmit pin (TXD) is connected to PC17. For both pins, the USART is peripheral B. In this
example, the state of the GPIO registers is assumed to be unknown. The two USART pins are
therefore first set to be controlled by the GPIO with output drivers disabled. The pins can then be
assured to be tri-stated while changing the Peripheral Mux Registers.

   // Set up pointer to GPIO, PORTC

   mov    R0, LO(AVR32_GPIO_ADDRESS + PORTC_OFFSET)

   orh    R0, HI(AVR32_GPIO_ADDRESS + PORTC_OFFSET)

   // Disable output drivers