Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
419
32072H–AVR32–10/2012
AT32UC3A3
21.8.2
Mode Register
Name: MR
Access Type: Read/Write
Offset:
0x04
Reset Value:
0x00000000
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default.
Otherwise, the following equation determines the delay:
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• LLB: Local Loopback Enable
1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is
internally connected on MOSI).
0: Local loopback path disabled.
• RXFIFOEN: FIFO in Reception Enable
1: The FIFO is used in reception (four characters can be stored in the SPI).
31
30
29
28
27
26
25
24
DLYBCS
23
22
21
20
19
18
17
16
-
-
-
-
PCS
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
LLB
RXFIFOEN
WDRBT-
MODFDIS
-
PCSDEC
PS
MSTR
Delay Between Chip Selects
DLYBCS
CLKSPI
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