Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
45
32072H–AVR32–10/2012
AT32UC3A3
Figure 7-3.
PLL with Control Logic and Filters
7.5.4.1
Enabling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency f
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency f
VCO
and the PLL
frequency f
PLL
:
if PLLDIV > 0
f
IN
= f
OSC
/2 • PLLDIV
f
VCO
= (PLLMUL+1)/(PLLDIV) • f
OSC
if PLLDIV = 0
f
IN
= f
OSC
f
VCO
= 2 • (PLLMUL+1) • f
OSC
Note:
Refer to Electrical Characteristics section for F
IN
and F
VCO
frequency range.
If PLLOPT[1] field is set to 0:
f
PLL
= f
VCO.
If PLLOPT[1] field is set to 1:
f
PLL
= f
VCO
/ 2
.
PLL
Output
Divider
0
1
Osc0 clock
Osc1 clock
PLLOSC
PLLEN
PLLOPT
PLLMUL
LOCK
Mask
PLL clock
Input
Divider
PLLDIV
Fin