Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
474
32072H–AVR32–10/2012
AT32UC3A3
23. Two-wire Master Interface (TWIM)
Rev.: 1.0.0.1
23.1
Features
•
Compatible with I
²
C standard
– Multi-master support
– Transfer speeds of 100 and 400 kbit/s
– 7- and 10-bit and General Call addressing
•
Compatible with SMBus standard
– Hardware Packet Error Checking (CRC) generation and verification with ACK control
– SMBus ALERT interface
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
•
Compatible with PMBus
•
Compatible with Atmel Two-wire Interface Serial Memories
•
DMA interface for reducing CPU load
•
Arbitrary transfer lengths, including 0 data bytes
•
Optional clock stretching if transmit or receive buffers not ready for data transfer
23.2
Overview
The Atmel Two-wire Master Interface (TWIM) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD
controller, and temperature sensor, to name a few. The TWIM is always a bus master and can
transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus
is performed internally and relinquishes the bus automatically if the bus arbitration is lost.
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD
controller, and temperature sensor, to name a few. The TWIM is always a bus master and can
transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus
is performed internally and relinquishes the bus automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
core clock frequencies.
lists the compatibility level of the Atmel Two-wire Interface in
Master Mode and a full I²C compatible device.
Note:
1. START + b000000001 + Ack + Sr
Table 23-1.
Atmel TWIM Compatibility with I²C Standard
I²C
Standard
Atmel TWIM
Standard-mode (100 kbit/s)
Supported
Fast-mode (400 kbit/s)
Supported
Fast-mode Plus (1 Mbit/s)
Supported
7- or 10-bits Slave Addressing
Supported
START BYTE
Not Supported
Repeated Start (Sr) Condition
Supported
ACK and NACK Management
Supported
Slope Control and Input Filtering (Fast mode)
Supported
Clock Stretching
Supported