Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK
clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR
describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be
selected through the Clock Prescaler field in CWGR (CWGR.EXP).

CWGR has the following fields:

LOW: Prescaled clock cycles in clock low count. Used to time T

LOW

 and T

BUF

.

HIGH: Prescaled clock cycles in clock high count. Used to time T

HIGH

.

STASTO: Prescaled clock cycles in clock high count. Used to time T

HD_STA

, T

SU_STA

, T

SU_STO

.

DATA: Prescaled clock cycles for data setup and hold count. Used to time T

HD_DAT

, T

SU_DAT

.

EXP: Specifies the clock prescaler setting.

Note that the total clock low time generated is the sum of T

HD_DAT

 + T

SU_DAT

 + T

LOW

.

Any slave or other bus master taking part in the transfer may extend the TWCK low period at any
time.

The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock low
time and the clock high time, but the TWCK rise and fall times are determined by the external cir-
cuitry (capacitive load, etc.).

Figure 23-5. Bus Timing Diagram

PRESCALER

CLK_TWIM

2

EXP

1

+

(

)

--------------------------

=

S

t

HD:STA

t LOW

t

SU:DAT

t HIGH

t

HD:DAT

t LOW

P

t

SU:STO

Sr

t

SU:STA

t

SU:DAT