Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Interrupt Mask Register (IMR.RXRDY) is set. If CSR.RXRDY is already set, RHR will be over-
written and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the
Overrun Error bit in IMR is set. Reading RHR will clear CSR.RXRDY, and writing a one to the
Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE. Refer to 

.

The USART supports five parity modes, selected by MR.PAR:

• Even parity

• Odd  parity

• Parity forced to zero (space)

• Parity forced to one (mark)

• No parity 

The PAR field also enables the Multidrop mode, see 

. If even par-

ity is selected (MR.PAR is 0x0), the parity bit will be zero if there is an even number of ones in
the data character, and one if there is an odd number. For odd parity the reverse applies. If
space or mark parity is chosen (MR.PAR is 0x2 or 0x3, respectively), the parity bit will always be
a zero or one, respectively. See 

The receiver will report parity errors in CSR.PARE, unless parity is disabled. An interrupt request
is generated if the PARE bit in the Interrupt Mask Register is set (IMR.PARE). Writing a one to
CR.RSTSTA will clear CSR.PARE. See 

Figure 25-8. Parity Error

Parity Bit Examples

A

0x41

0100 0001

1

0

1

0

-

V

0x56

0101 0110

1

0

1

0

-

R

0x52

0101 0010

0

1

1

0

-

D0

D1

D2

D3

D4

D5

D6

D7

RXD

Start 

Bit

Bad

Parity

Bit

Stop

Bit

Baud Rate

 Clock

Write

CR

PARE

RXRDY

RSTSTA = 1