Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

A break condition is assumed when incoming data, parity, and stop bits are zero. This corre-
sponds to a framing error, but CSR.FRAME will remain zero while the Break Received/End of
Break bit (CSR.RXBRK) is set. An interrupt request is generated if the Breadk Received/End of
Break bit in the Interrupt Mask Register is set (IMR.RXBRK). Writing a one to CR.RSTSTA will
clear CSR.RXBRK. An end of break will also set CSR.RXBRK, and is assumed when TX is high
for at least 2/16 of a bit period in asynchronous mode, or when a high level is sampled in syn-
chronous mode.

The baud rate generator provides the bit period clock named the Baud Rate Clock to both
receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider
field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,
and if BRGR.CD is one, the divider is bypassed and inactive. The Clock Selection field in the
Mode Register (MR.USCLKS) selects clock source between:

• CLK_USART (internal clock, refer to Power Manager chapter for details)

• CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)

• CLK (external clock, available on the CLK pin)

If the external clock CLK is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.

Figure 25-13. Baud Rate Generator

If the USART is configured to operate in asynchronous mode (MR.SYNC is zero), the selected
clock is divided by the BRGR.CD value before it is provided to the receiver as a sampling clock.
Depending on the Oversampling Mode bit (MR.OVER) value, the clock is then divided by either
8 (MR.OVER=1), or 16 (MR.OVER=0). The baud rate is calculated with the following formula:

16-bit Counter

CD

USCLKS

CD

CLK_USART

CLK_USART/DIV

Reserved

CLK

SYNC

SYNC

USCLKS= 3

FIDI

OVER

Sampling

Divider

BaudRate

Clock

Sampling

Clock

1

0

0

CLK

0
1

2

3

>1

1

1

0

0

8 2

–

(

)CD

(

)

------------------------------------------------

=