Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
568
32072H–AVR32–10/2012
AT32UC3A3
25.6.9.3
IrDA Demodulator
The demodulator depends on an 8-bit down counter loaded with the value in the IRDA_Filter
field in the IrDA Filter Register (IFR.IRDA_FILTER). When a falling edge on RXD is detected,
the counter starts decrementing at CLK_USART speed. If a rising edge on RXD is detected , the
counter stops and is reloaded with the IrD Filter value. If no rising edge has been detected when
the counter reaches zero, the receiver input is pulled low during one bit period, see
field in the IrDA Filter Register (IFR.IRDA_FILTER). When a falling edge on RXD is detected,
the counter starts decrementing at CLK_USART speed. If a rising edge on RXD is detected , the
counter stops and is reloaded with the IrD Filter value. If no rising edge has been detected when
the counter reaches zero, the receiver input is pulled low during one bit period, see
. Writing a one to the Infrared Receive Line Filter bit (MR.FILTER), enables a noise filter that,
instead of using just one sample, will choose the majority value from three consecutive samples.
Figure 25-26. IrDA Demodulator Operations
25.6.10
LIN Mode
The USART features a Local Interconnect Network (LIN) 1.3 and 2.0 compliant mode, embed-
ding full error checking and reporting, automatic frame processing with up to 256 data bytes,
customizable response data lengths, and requiring minimal CPU resources. The LIN mode is
enabled by writing 0xA (master) or 0xB (slave) to MR.MODE.
ding full error checking and reporting, automatic frame processing with up to 256 data bytes,
customizable response data lengths, and requiring minimal CPU resources. The LIN mode is
enabled by writing 0xA (master) or 0xB (slave) to MR.MODE.
3 686 400
38 400
6
0.00%
4.88
20 000 000
38 400
33
1.38%
4.88
32 768 000
38 400
53
0.63%
4.88
40 000 000
38 400
65
0.16%
4.88
3 686 400
19 200
12
0.00%
9.77
20 000 000
19 200
65
0.16%
9.77
32 768 000
19 200
107
0.31%
9.77
40 000 000
19 200
130
0.16%
9.77
3 686 400
9 600
24
0.00%
19.53
20 000 000
9 600
130
0.16%
19.53
32 768 000
9 600
213
0.16%
19.53
40 000 000
9 600
260
0.16%
19.53
3 686 400
2 400
96
0.00%
78.13
20 000 000
2 400
521
0.03%
78.13
32 768 000
2 400
853
0.04%
78.13
Table 25-13. IrDA Baud Rate Error (Continued)
Peripheral Clock
Baud Rate
CD
Baud Rate Error
Pulse Time
CLK_USART
RXD
Counter
Value
Receiver
Input
6
5
4
6
3
Pulse
Rejected
2
6
4
5
3
2
1
0
Pulse
Accepted
Driven Low During 16 Baud Rate Clock Cycles