Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The baud rate generator operates as described in 

, with the following requirements:

In SPI Master Mode:

• External clock CLK must not be selected as clock (the Clock Selection field (MR.USCLKS) 

must not equal 0x3).

• The USART must drive the CLK pin (MR.CLKO must be one).

• The BRGR.CD field must be at least 0x4.

• If the internal divided clock, CLK_USART/DIV, is selected (MR.USCLKS is one), the value in 

BRGR.CD must be even, ensuring a 50:50 duty cycle. 

In SPI Slave Mode:

• The frequency of the external clock CLK must be at least four times lower than the system 

clock.

Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL), and
SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits are
shifted and sampled, resulting in four non-interoperable protocol modes, see 

. If

MR.CPOL is zero, the inactive state value of CLK is logic level zero, and if MR.CPOL is one, the
inactive state value of CLK is logic level one. If MR.CPHA is zero, data is changed on the lead-
ing edge of CLK, and captured on the following edge of CLK. If MR.CPHA is one, data is
captured on the leading edge of CLK, and changed on the following edge of CLK. A mas-
ter/slave pair must use the same configuration, and the master must be reconfigured if it is to
communicate with slaves using different configurations. See 

.

Table 25-16. SPI Bus Protocol Modes

0

1

0

0

0

1

1

1

2

1

0

3