Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

Figure 25-46. Start Frame Delimiter

The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery
system that allows for sub-optimal clock drifts without further user intervention. Drift compensa-
tion is only available in 16x oversampling mode (MR.OVER is zero). If the RXD event is one 16

th

clock cycle from the expected edge, it is considered as normal jitter and no corrective action will
be taken. If the event is two to four 16

th

’s early, the current period will be shortened by a 16

th

. If

the event is two to three 16

th

’s after the expected edge, the current period will be prolonged by a

16

th

.

Figure 25-47. Bit Resynchronization

The Manchester decoder can detect selectable preamble sequences and start frame delimiters.
The Receiver Manchester Polarity bit in the 

(MAN.RX_MPOL) selects input stream polarity. The Receiver Preamble Length field
(MAN.RX_PL) specifies the length characteristics of detectable preambles. If MAN.RX_PL is
zero, the preamble pattern detection will be disabled. The Receiver Preamble Pattern field
(MAN.RX_PP) selects the pattern to be detected. See 

 for available preamble pat-

terns. 

 illustrates two types of Manchester preamble pattern mismatches.

Manchester

encoded

data

Txd

SFD

DATA

One bit start frame delimiter

Preamble Length 

is set to 0

Manchester

encoded

data

Txd

SFD

DATA

Command Sync

start frame delimiter

Manchester

encoded

data

Txd

SFD

DATA

Data Sync

start frame delimiter

RXD

Oversampling

 16x Clock

Sampling 

point

Expected edge

Tolerance

Synchro.

Jump

Sync

Jump

Synchro.

Error

Synchro.

Error