Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
622
32072H–AVR32–10/2012
AT32UC3A3
26.1
Module Configuration
The specific configuration for each USART instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
26.1.1
Clock Connections
Each USART can be connected to an internally divided clock:
Table 26-1.
Module Configuration
Feature
USART0
USART2
USART3
USART1
SPI Logic
Implemented
Implemented
LIN Logic
Implemented
Implemented
Manchester Logic
Not Implemented
Implemented
Modem Logic
Not Implemented
Implemented
IRDA Logic
Not Implemented
Implemented
RS485 Logic
Not Implemented
Implemented
Fractional Baudrate
Implemented
Implemented
ISO7816
Not Implemented
Implemented
DIV value for divided CLK_USART
8
8
Receiver Time-out Counter Size
(Size of the RTOR.TO field)
8-bits
17-bits
Table 26-2.
Module Clock Name
Module name
Clock name
Description
USART0
CLK_USART0
Peripheral Bus clock from the PBA clock domain
USART1
CLK_USART1
Peripheral Bus clock from the PBA clock domain
USART2
CLK_USART2
Peripheral Bus clock from the PBA clock domain
USART3
CLK_USART3
Peripheral Bus clock from the PBA clock domain
Table 26-3.
USART Clock Connections
USART
Source
Name
Connection
0
Internal
CLK_DIV
PBA Clock / 8 (CLK_PBA_USART_DIV)
1
PBA Clock / 8 (CLK_PBA_USART_DIV)
2
PBA Clock / 8 (CLK_PBA_USART_DIV)
3
PBA Clock / 8 (CLK_PBA_USART_DIV)