Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
625
32072H–AVR32–10/2012
AT32UC3A3
27.3
Block Diagram
The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port
RAM (DPRAM).
RAM (DPRAM).
The UTMI transceiver requires an external 12MHz clock as a reference to its internal 480 MHz
PLL. The internal 480MHz PLL is used to clock an internal DLL module to recover the USB dif-
ferential data at 480Mbit/s.
PLL. The internal 480MHz PLL is used to clock an internal DLL module to recover the USB dif-
ferential data at 480Mbit/s.
Figure 27-1. USBB Block Diagram
1
PEP1
512 bytes
2
2
PEP2
512 bytes
2
3
PEP3
256 bytes
1
Table 27-2.
Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Pipe/Endpoint
Mnemonic
Size
Nb. Banks
HSB Mux
Slave
Master
HSB
PB
DMA
HSB0
HSB1
Slave
Local HSB
Slave
Interface
User
Interface
Interface
USB
2.0 Core
DPRAM
PEP
Allocation
USB_VBUS
DMFS
DPFS
USB_ID
USB_VBOF
I/O
Controller
UTMI
DMHS
DPHS
Master
GCLK_USBB