Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written which acknowledges or not the bank when it is full.

The endpoint must be configured first.

The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers
an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.

TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt, what has no effect on the endpoint FIFO.

The user then writes into the FIFO (see 

) and write a one to the FIFO Control Clear (FIFOCONC) bit in

UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN end-
point is composed of multiple banks, this also switches to the next bank. The TXINI and
FIFOCON bits are updated in accordance with the status of the next bank.

TXINI shall always be cleared before clearing FIFOCON.

The RWALL bit is set when the current bank is not full, i.e. the software can write further data
into the FIFO.

Figure 27-16. Example of an IN Endpoint with 1 Data Bank

IN

DATA

(bank 0)

ACK

TXINI

FIFOCON

HW

write data to CPU

BANK 0

SW

SW

SW

SW

IN

NAK

write data to CPU

BANK 0