Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

• The NAKed OUT Interrupt (NAKOUTI)

• The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) if the high-bandwidth 

isochronous feature is supported by the device (see the UFEATURES register for this)

• The NAKed IN Interrupt (NAKINI)

• The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) if the high-

bandwidth isochronous feature is supported by the device (see the UFEATURES register for 
this)

• The Overflow Interrupt (OVERFI)

• The STALLed Interrupt (STALLEDI)

• The CRC Error Interrupt (CRCERRI)

• The Transaction error (ERRORTRANS) interrupt if the high-bandwidth isochronous feature is 

supported by the device (see the UFEATURES register for this)

The processing device DMA interrupts are:

• The End of USB Transfer Status (EOTSTA) interrupt

• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt

• The Descriptor Loaded Status (DESCLDSTA) interrupt

There is no exception device DMA interrupt.

When written to one, the UDCON.TSTPCKT bit switches the USB device controller in a “test
packet”mode:

The transceiver repeatedly transmit the packet stored in the current bank. TSTPCKT must be
written to zero to exit the “test-packet” mode. The endpoint shall be reset by software after a
“test-packet” mode.

This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic
waveform specifications.

The flow control used to send the packets is as follows:

• TSTPCKT=1;

• Store data in an endpoint bank

• Write a zero to FifoCON bit

To stop the test-packet mode, just write a zero to the TSTPCKT bit.